
PIC16(L)F1826/2
7
DS4
1391D-page
6
20
11
M
ic
rochip
T
e
chnology
In
c.
TABLE 1:
18/20/28-PIN SUMMARY (PIC16(L)F1826/27)
I/O
18
-P
in
P
D
IP
/S
OIC
2
0
-P
in
S
O
P
28
-P
in
QF
N/UQ
F
N
ANSEL
A/
D
Re
fe
re
n
c
e
Ca
p
Se
n
s
e
C
o
m
p
ar
at
or
SR
La
tc
h
Ti
m
e
rs
CCP
EUSART
MS
S
P
In
te
rru
pt
Mo
d
u
la
to
r
Pu
ll-
u
p
Ba
s
ic
RA0
17
19
23
Y
AN0
—
CPS0
C12IN0-
—
SDO2(2)
—
N
—
RA1
18
20
24
Y
AN1
—
CPS1
C12IN1-
—
SS2(2)
—
N
—
RA2
1
26
Y
AN2
VREF-
DACOUT
CPS2
C12IN2-
C12IN+
—
N
—
RA3
2
27
Y
AN3
VREF+
CPS3
C12IN3-
C1IN+
C1OUT
SRQ
—
CCP3(2)
—
N
—
RA4
3
28
Y
AN4
—
CPS4
C2OUT
SRNQ
T0CKI
CCP4(2)
—
N
—
RA5
4
1
N
—
SS1(1)
—
Y(3)
MCLR, VPP
RA6
15
17
20
N
—
P1D(1)
P2B(1,2)
—
SDO1(1)
—
N
OSC2
CLKOUT
CLKR
RA7
16
18
21
N
—
P1C(1)
CCP2(1,2)
P2A(1,2)
—
N
OSC1
CLKIN
RB0
6
7
N
—
SRI
T1G
CCP1(1)
P1A(1)
FLT0
—
INT
IOC
—
Y
—
RB1
7
8
Y
AN11
—
CPS11
—
RX(1,4)
DT(1,4)
SDA1
SDI1
IOC
—
Y
—
RB2
8
9
Y
AN10
—
CPS10
—
RX(1),DT(1)
TX(1,4)
CK(1,4)
SDA2(2)
SDI2(2)
SDO1(1,4)
IOC
MDMIN
Y
—
RB3
9
10
Y
AN9
—
CPS9
—
CCP1(1,4)
P1A(1,4)
—
IOC
MDOUT
Y
—
RB4
10
11
12
Y
AN8
—
CPS8
—
SCL1
SCK1
IOC
MDCIN2
Y
—
RB5
11
12
13
Y
AN7
—
CPS7
—
P1B
TX(1)
CK(1)
SCL2(2)
SCK2(2)
SS1(1,4)
IOC
—
Y
—
RB6
12
13
15
Y
AN5
—
CPS5
—
T1CKI
T1OSI
P1C(1,4)
CCP2(1,2,4)
P2A(1,2,4)
—
IOC
—
Y
ICSPCLK/
ICDCLK
RB7
13
14
16
Y
AN6
—
CPS6
—
T1OSO
P1D(1,4)
P2B(1,2,4)
—
IOC
MDCIN1
Y
ICSPDAT/
ICDDAT
VDD
14
15,16 17,19
—
VDD
Vss
5
5,6
3,5
———
—
——
—
——
VSS
Note 1:
Pin functions can be moved using the APFCON0 or APFCON1 register.
2:
Functions are only available on the PIC16(L)F1827.
3:
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
4:
Default function location.